00001
00008 #ifndef _SYS_H_
00009 #define _SYS_H_
00010
00019 #define EXC_INT 0
00020 #define EXC_MOD 1
00021 #define EXC_TLBL 2
00022 #define EXC_TLBS 3
00023 #define EXC_ADEL 4
00024 #define EXC_ADES 5
00025 #define EXC_IBE 6
00026 #define EXC_DBE 7
00027 #define EXC_SYS 8
00028 #define EXC_BP 9
00029 #define EXC_RI 10
00030 #define EXC_CPU 11
00031 #define EXC_OV 12
00032 #define EXC_TR 13
00033 #define EXC_WATCH 23
00034
00049 #define read_cp0_reg(regno) \
00050 ({ int __res; \
00051 asm volatile ( \
00052 " .set push\n" \
00053 " .set noreorder\n" \
00054 " nop\n" \
00055 " mfc0 %0, $"#regno"\n" \
00056 " .set pop\n" \
00057 : "=r" (__res)); \
00058 __res; })
00059
00060 #define read_cp0_badvaddr() read_cp0_reg(8)
00061 #define read_cp0_count() read_cp0_reg(9)
00062 #define read_cp0_compare() read_cp0_reg(11)
00063 #define read_cp0_status() read_cp0_reg(12)
00064 #define read_cp0_cause() read_cp0_reg(13)
00065 #define read_cp0_epc() read_cp0_reg(14)
00066 #define read_cp0_xcontext() read_cp0_reg(20)
00067 #define read_cp0_eepc() read_cp0_reg(30)
00068
00069
00070 #define write_cp0_reg(regno, i) \
00071 asm volatile ( \
00072 " .set push\n" \
00073 " .set noreorder\n" \
00074 " nop\n" \
00075 " mtc0 %0, $"#regno"\n" \
00076 " .set pop\n" \
00077 :: "r" (i) );
00078
00079 #define write_cp0_index(val) write_cp0_reg(0, val)
00080 #define write_cp0_entrylo0(val) write_cp0_reg(2, val)
00081 #define write_cp0_entrylo1(val) write_cp0_reg(3, val)
00082 #define write_cp0_pagemask(val) write_cp0_reg(5, val)
00083 #define write_cp0_wired(val) write_cp0_reg(6, val)
00084 #define write_cp0_count(val) write_cp0_reg(9, val)
00085 #define write_cp0_entryhi(val) write_cp0_reg(10, val)
00086 #define write_cp0_compare(val) write_cp0_reg(11, val)
00087 #define write_cp0_status(val) write_cp0_reg(12, val)
00088 #define write_cp0_cause(val) write_cp0_reg(13, val)
00089 #define write_cp0_epc(val) write_cp0_reg(14, val)
00090 #define write_cp0_eepc(val) write_cp0_reg(30, val)
00091
00098 #define TLBWI() \
00099 asm volatile ( \
00100 " tlbwi\n" \
00101 );
00102
00108 #define TLBWR() \
00109 asm volatile ( \
00110 " tlbwr\n" \
00111 );
00112
00113
00131 #define cp0_index_index_mask 0x0000003f
00132 #define cp0_index_res_mask 0x7fffffc0
00133 #define cp0_index_p_mask 0x80000000
00134
00135 #define cp0_index_index_shift 0
00136 #define cp0_index_res_shift 6
00137 #define cp0_index_p_shift 31
00138
00139 #define cp0_index_index(r) \
00140 (((r) & cp0_index_index_mask) >> cp0_index_index_shift)
00141 #define cp0_index_res(r) \
00142 (((r) & cp0_index_res_mask) >> cp0_index_res_shift)
00143 #define cp0_index_p(r) \
00144 (((r) & cp0_index_p_mask) >> cp0_index_p_shift)
00145
00158 #define cp0_random_random_mask 0x0000003f
00159 #define cp0_random_res_mask 0xffffffc0
00160
00161 #define cp0_random_random_shift 0
00162 #define cp0_random_res_shift 6
00163
00164 #define cp0_random_random(r) \
00165 (((r) & cp0_random_random_mask) >> cp0_random_random_shift)
00166 #define cp0_random_res(r) \
00167 (((r) & cp0_random_res_mask) >> cp0_random_res_shift)
00168
00196 #define cp0_status_ie_mask 0x00000001
00197 #define cp0_status_exl_mask 0x00000002
00198 #define cp0_status_erl_mask 0x00000004
00199 #define cp0_status_ksu_mask 0x00000018
00200 #define cp0_status_ux_mask 0x00000020
00201 #define cp0_status_sx_mask 0x00000040
00202 #define cp0_status_kx_mask 0x00000080
00203 #define cp0_status_im_mask 0x0000ff00
00204 # define cp0_status_im0_mask 0x00000100
00205 # define cp0_status_im1_mask 0x00000200
00206 # define cp0_status_im2_mask 0x00000400
00207 # define cp0_status_im3_mask 0x00000800
00208 # define cp0_status_im4_mask 0x00001000
00209 # define cp0_status_im5_mask 0x00002000
00210 # define cp0_status_im6_mask 0x00004000
00211 # define cp0_status_im7_mask 0x00008000
00212 #define cp0_status_de_mask 0x00010000
00213 #define cp0_status_ce_mask 0x00020000
00214 #define cp0_status_ch_mask 0x00040000
00215 #define cp0_status_res1_mask 0x00080000
00216 #define cp0_status_sr_mask 0x00100000
00217 #define cp0_status_ts_mask 0x00200000
00218 #define cp0_status_bev_mask 0x00400000
00219 #define cp0_status_res2_mask 0x01800000
00220 #define cp0_status_re_mask 0x02000000
00221 #define cp0_status_fr_mask 0x04000000
00222 #define cp0_status_rp_mask 0x08000000
00223 #define cp0_status_cu0_mask 0x10000000
00224 #define cp0_status_cu1_mask 0x20000000
00225 #define cp0_status_cu2_mask 0x40000000
00226 #define cp0_status_cu3_mask 0x80000000
00227 #define cp0_status_cu_mask 0xf0000000
00228
00229 #define cp0_status_ie_shift 0
00230 #define cp0_status_exl_shift 1
00231 #define cp0_status_erl_shift 2
00232 #define cp0_status_ksu_shift 3
00233 #define cp0_status_ux_shift 5
00234 #define cp0_status_sx_shift 6
00235 #define cp0_status_kx_shift 7
00236 #define cp0_status_im_shift 8
00237 #define cp0_status_de_shift 16
00238 #define cp0_status_ce_shift 17
00239 #define cp0_status_ch_shift 18
00240 #define cp0_status_res1_shift 19
00241 #define cp0_status_sr_shift 20
00242 #define cp0_status_ts_shift 21
00243 #define cp0_status_bev_shift 22
00244 #define cp0_status_res2_shift 23
00245 #define cp0_status_re_shift 25
00246 #define cp0_status_fr_shift 26
00247 #define cp0_status_rp_shift 27
00248 #define cp0_status_cu0_shift 28
00249 #define cp0_status_cu1_shift 29
00250 #define cp0_status_cu2_shift 30
00251 #define cp0_status_cu3_shift 31
00252 #define cp0_status_cu_shift 28
00253
00254 #define cp0_status_ie(r) \
00255 (((r) & cp0_status_ie_mask) >> cp0_status_ie_shift)
00256 #define cp0_status_exl(r) \
00257 (((r) & cp0_status_exl_mask) >> cp0_status_exl_shift)
00258 #define cp0_status_erl(r) \
00259 (((r) & cp0_status_erl_mask) >> cp0_status_erl_shift)
00260 #define cp0_status_ksu(r) \
00261 (((r) & cp0_status_ksu_mask) >> cp0_status_ksu_shift)
00262 #define cp0_status_ux(r) \
00263 (((r) & cp0_status_ux_mask) >> cp0_status_ux_shift)
00264 #define cp0_status_sx(r) \
00265 (((r) & cp0_status_sx_mask) >> cp0_status_sx_shift)
00266 #define cp0_status_kx(r) \
00267 (((r) & cp0_status_kx_mask) >> cp0_status_kx_shift)
00268 #define cp0_status_im(r) \
00269 (((r) & cp0_status_im_mask) >> cp0_status_im_shift)
00270 #define cp0_status_de(r) \
00271 (((r) & cp0_status_de_mask) >> cp0_status_de_shift)
00272 #define cp0_status_ce(r) \
00273 (((r) & cp0_status_ce_mask) >> cp0_status_ce_shift)
00274 #define cp0_status_ch(r) \
00275 (((r) & cp0_status_ch_mask) >> cp0_status_ch_shift)
00276 #define cp0_status_res1(r) \
00277 (((r) & cp0_status_res1_mask) >> cp0_status_res1_shift)
00278 #define cp0_status_sr(r) \
00279 (((r) & cp0_status_sr_mask) >> cp0_status_sr_shift)
00280 #define cp0_status_ts(r) \
00281 (((r) & cp0_status_ts_mask) >> cp0_status_ts_shift)
00282 #define cp0_status_bev(r) \
00283 (((r) & cp0_status_bev_mask) >> cp0_status_bev_shift)
00284 #define cp0_status_res2(r) \
00285 (((r) & cp0_status_res2_mask) >> cp0_status_res2_shift)
00286 #define cp0_status_re(r) \
00287 (((r) & cp0_status_re_mask) >> cp0_status_re_shift)
00288 #define cp0_status_fr(r) \
00289 (((r) & cp0_status_fr_mask) >> cp0_status_fr_shift)
00290 #define cp0_status_rp(r) \
00291 (((r) & cp0_status_rp_mask) >> cp0_status_rp_shift)
00292 #define cp0_status_cu0(r) \
00293 (((r) & cp0_status_cu0_mask) >> cp0_status_cu0_shift)
00294 #define cp0_status_cu1(r) \
00295 (((r) & cp0_status_cu1_mask) >> cp0_status_cu1_shift)
00296 #define cp0_status_cu2(r) \
00297 (((r) & cp0_status_cu2_mask) >> cp0_status_cu2_shift)
00298 #define cp0_status_cu3(r) \
00299 (((r) & cp0_status_cu3_mask) >> cp0_status_cu3_shift)
00300 #define cp0_status_cu(r) \
00301 (((r) & cp0_status_cu_mask) >> cp0_status_cu_shift)
00302
00313 #define cp0_entryhi_asid_mask 0x000000ff
00314 #define cp0_entryhi_res1_mask 0x00001f00
00315 #define cp0_entryhi_vpn2_mask 0xffffe000
00316
00317 #define cp0_entryhi_asid_shift 0
00318 #define cp0_entryhi_res1_shift 8
00319 #define cp0_entryhi_vpn2_shift 13
00320
00321 #define cp0_entryhi_asid(r) \
00322 (((r) & cp0_entryhi_asid_mask) >> cp0_entryhi_asid_shift)
00323 #define cp0_entryhi_res1(r) \
00324 (((r) & cp0_entryhi_res1_mask) >> cp0_entryhi_res1_shift)
00325 #define cp0_entryhi_vpn2(r) \
00326 (((r) & cp0_entryhi_vpn2_mask) >> cp0_entryhi_vpn2_shift)
00327
00338 #define cp0_entrylo_g_mask 0x00000001
00339 #define cp0_entrylo_v_mask 0x00000002
00340 #define cp0_entrylo_d_mask 0x00000004
00341 #define cp0_entrylo_c_mask 0x00000038
00342 #define cp0_entrylo_pfn_mask 0x3fffffc0
00343 #define cp0_entrylo_res1_mask 0xc0000000
00344
00345 #define cp0_entrylo_g_shift 0
00346 #define cp0_entrylo_v_shift 1
00347 #define cp0_entrylo_d_shift 2
00348 #define cp0_entrylo_c_shift 3
00349 #define cp0_entrylo_pfn_shift 6
00350 #define cp0_entrylo_res1_shift 30
00351
00352 #define cp0_entrylo0_g(r) \
00353 (((r) & cp0_entrylo_g_mask) >> cp0_entrylo_g_shift)
00354 #define cp0_entrylo0_v(r) \
00355 (((r) & cp0_entrylo_v_mask) >> cp0_entrylo_v_shift)
00356 #define cp0_entrylo0_d(r) \
00357 (((r) & cp0_entrylo_d_mask) >> cp0_entrylo_d_shift)
00358 #define cp0_entrylo0_c(r) \
00359 (((r) & cp0_entrylo_c_mask) >> cp0_entrylo_c_shift)
00360 #define cp0_entrylo0_pfn(r) \
00361 (((r) & cp0_entrylo_pfn_mask) >> cp0_entrylo_pfn_shift)
00362 #define cp0_entrylo0_res1(r) \
00363 (((r) & cp0_entrylo_res1_mask) >> cp0_entrylo_res1_shift)
00364
00365 #define cp0_entrylo1_g \
00366 (((r) & cp0_entrylo_g_mask) >> cp0_entrylo_g_shift)
00367 #define cp0_entrylo1_v \
00368 (((r) & cp0_entrylo_v_mask) >> cp0_entrylo_v_shift)
00369 #define cp0_entrylo1_d \
00370 (((r) & cp0_entrylo_d_mask) >> cp0_entrylo_d_shift)
00371 #define cp0_entrylo1_c \
00372 (((r) & cp0_entrylo_c_mask) >> cp0_entrylo_c_shift)
00373 #define cp0_entrylo1_pfn \
00374 (((r) & cp0_entrylo_pfn_mask) >> cp0_entrylo_pfn_shift)
00375 #define cp0_entrylo1_res1 \
00376 (((r) & cp0_entrylo_res1_mask) >> cp0_entrylo_res1_shift)
00377
00390 #define cp0_wired_w_mask 0x0000001f
00391 #define cp0_wired_res1_mask 0xffffffe0
00392
00393 #define cp0_wired_w_shift 0
00394 #define cp0_wired_res1_shift 6
00395
00396 #define cp0_wired_w(r) \
00397 (((r) & cp0_wired_w_mask) >> cp0_wired_w_shift)
00398 #define cp0_wired_res1(r) \
00399 (((r) & cp0_wired_res1_mask) >> cp0_wired_res1_shift)
00400
00416 #define cp0_context_res1_mask 0x0000000f
00417 #define cp0_context_badvpn2_mask 0x007ffff0
00418 #define cp0_context_ptebase_mask 0xff800000
00419
00420 #define cp0_context_res1_shift 0
00421 #define cp0_context_badvpn2_shift 4
00422 #define cp0_context_ptebase_shift 23
00423
00424 #define cp0_context_res1(r) \
00425 (((r) & cp0_context_res1_mask) >> cp0_context_res1_shift)
00426 #define cp0_context_badvpn2(r) \
00427 (((r) & cp0_context_badvpn2_mask) >> cp0_context_badvpn2_shift)
00428 #define cp0_context_ptebase(r) \
00429 (((r) & cp0_context_ptebase_mask) >> cp0_context_ptebase_shift)
00430
00442 #define cp0_pagemask_res1_mask 0x00001fff
00443 #define cp0_pagemask_mask_mask 0x01ffe000
00444 #define cp0_pagemask_res2_mask 0xfe000000
00445
00446 #define cp0_pagemask_res1_shift 0
00447 #define cp0_pagemask_mask_shift 13
00448 #define cp0_pagemask_res2_shift 25
00449
00450 #define cp0_pagemask_res1(r) \
00451 (((r) & cp0_pagemask_res1_mask) >> cp0_pagemask_res1_shift)
00452 #define cp0_pagemask_mask(r) \
00453 (((r) & cp0_pagemask_mask_mask) >> cp0_pagemask_mask_shift)
00454 #define cp0_pagemask_res2(r) \
00455 (((r) & cp0_pagemask_res2_mask) >> cp0_pagemask_res2_shift)
00456
00457 #define PAGEMASK_4K (0x000 << cp0_pagemask_mask_shift)
00458 #define PAGEMASK_16K (0x003 << cp0_pagemask_mask_shift)
00459 #define PAGEMASK_64K (0x00f << cp0_pagemask_mask_shift)
00460 #define PAGEMASK_256K (0x03f << cp0_pagemask_mask_shift)
00461 #define PAGEMASK_1M (0x0ff << cp0_pagemask_mask_shift)
00462 #define PAGEMASK_4M (0x3ff << cp0_pagemask_mask_shift)
00463 #define PAGEMASK_16M (0xfff << cp0_pagemask_mask_shift)
00464
00475 #define cp0_count_count_mask 0xffffffff
00476 #define cp0_count_count_shift 0
00477 #define cp0_count_count(r) \
00478 (((r) & cp0_count_count_mask) >> cp0_count_count_shift)
00479
00489 #define cp0_badvaaddr_badvaaddr_mask 0xffffffff
00490 #define cp0_badvaaddr_badvaaddr_shift 0
00491 #define cp0_badvaaddr_badvaaddr(r) \
00492 (((r) & cp0_badvaaddr_badvaaddr_mask) >> cp0_badvaaddr_badvaaddr_shift)
00493
00508 #define cp0_compare_compare_mask 0xffffffff
00509 #define cp0_compare_compare_shift 0
00510 #define cp0_compare_compare(r) \
00511 (((r) & cp0_compare_compare_mask) >> cp0_compare_compare_shift)
00512
00527 #define cp0_epc_epc_mask 0xffffffff
00528 #define cp0_epc_epc_shift 0
00529 #define cp0_epc_epc(r) \
00530 (((r) & cp0_epc_epc_mask) >> cp0_epc_epc_shift)
00531
00552 #define cp0_cause_res1_mask 0x00000003
00553 #define cp0_cause_exccode_mask 0x0000007c
00554 #define cp0_cause_res2_mask 0x00000080
00555 #define cp0_cause_ip_mask 0x0000ff00
00556 # define cp0_cause_ip0_mask 0x00000100
00557 # define cp0_cause_ip1_mask 0x00000200
00558 # define cp0_cause_ip2_mask 0x00000400
00559 # define cp0_cause_ip3_mask 0x00000800
00560 # define cp0_cause_ip4_mask 0x00001000
00561 # define cp0_cause_ip5_mask 0x00002000
00562 # define cp0_cause_ip6_mask 0x00004000
00563 # define cp0_cause_ip7_mask 0x00008000
00564 #define cp0_cause_res3_mask 0x0fff0000
00565 #define cp0_cause_ce_mask 0x30000000
00566 #define cp0_cause_bd_mask 0x80000000
00567 #define cp0_cause_res4_mask 0x40000000
00568
00569 #define cp0_cause_ce_cu1 0x10000000
00570 #define cp0_cause_ce_cu2 0x20000000
00571 #define cp0_cause_ce_cu3 0x30000000
00572
00573 #define cp0_cause_res1_shift 0
00574 #define cp0_cause_exccode_shift 2
00575 #define cp0_cause_res2_shift 7
00576 #define cp0_cause_ip_shift 8
00577 # define cp0_cause_ip0_shift 8
00578 # define cp0_cause_ip1_shift 9
00579 # define cp0_cause_ip2_shift 10
00580 # define cp0_cause_ip3_shift 11
00581 # define cp0_cause_ip4_shift 12
00582 # define cp0_cause_ip5_shift 13
00583 # define cp0_cause_ip6_shift 14
00584 # define cp0_cause_ip7_shift 15
00585 #define cp0_cause_res3_shift 16
00586 #define cp0_cause_ce_shift 28
00587 #define cp0_cause_res4_shift 30
00588 #define cp0_cause_bd_shift 31
00589
00590 #define cp0_cause_res1(r) \
00591 (((r) & cp0_cause_res1_mask) >> cp0_cause_res1_shift)
00592 #define cp0_cause_exccode(r) \
00593 (((r) & cp0_cause_exccode_mask) >> cp0_cause_exccode_shift)
00594 #define cp0_cause_res2(r) \
00595 (((r) & cp0_cause_res2_mask) >> cp0_cause_res2_shift)
00596 #define cp0_cause_ip(r) \
00597 (((r) & cp0_cause_ip_mask) >> cp0_cause_ip_shift)
00598 #define cp0_cause_res3(r) \
00599 (((r) & cp0_cause_res3_mask) >> cp0_cause_res3_shift)
00600 #define cp0_cause_ce(r) \
00601 (((r) & cp0_cause_ce_mask) >> cp0_cause_ce_shift)
00602 #define cp0_cause_res4(r) \
00603 (((r) & cp0_cause_res4_mask) >> cp0_cause_res4_shift)
00604 #define cp0_cause_bd(r) \
00605 (((r) & cp0_cause_bd_mask) >> cp0_cause_bd_shift)
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00622 #define cp0_lladdr_lladdr cp0_lladdr
00623
00634 #define OM_USER 0x00000000
00635 #define OM_KSEG0 0x80000000
00636 #define OM_KSEG1 0xa0000000
00637 #define OM_KSSEG 0xc0000000
00638 #define OM_KSEG3 0xe0000000
00639
00649 void switch_cpu_context (void **kst1, void *kst2);
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00683 #endif